1 of 6 pa7128 or global clocks, resets, presets, clock polarity and other special features, making the pa7128 suitable for a variety of combinatorial, synchronous and asynchronous logic appli- cations. the pa7128 offers pin compatibility and super-set functionality to popular 28-pin plds, such as the 26v12. thus, designs that exceed the architectures of such devices can be expanded upon. the pa7128 supports speeds as fast as 9ns/15ns (tpdi/tpdx) and 83.3mhz (f max ) at moderate power consumption 105ma (75ma typical). packaging includes 28-pin dip, soic and plcc (see fig- ure 1). development and programming support for the pa7128 is provided by ict and popular third-party develop- ment tool manufacturers. pa7128 peel tm array programmable electrically erasable logic array n cmos electrically erasable technology - reprogrammable in 28-pin dip, soic and plcc packages n versatile logic array architecture - 12 i/os, 14 inputs, 36 registers/latches - up to 36 logic cell output functions - pla structure with true product-term sharing - logic functions and registers can be i/o-buried n flexible logic cell - up to 3 output functions per logic cell - d,t and jk registers with special features - independent or global clo cks, resets, presets, clock polarity and output enables - sum-of-products logic for output enables n high-speed commercial and industrial versions - as fast as 9ns/15ns (tpdi/tpdx), 83.3mhz (f max ) - industrial grade available for 4.5 to 5.5v vcc and -40 to +85 c temperatures n ideal for combinatorial, synchronous and asyn- chronous logic applications - integration of multiple plds and random logic - buried counters, complex state-machines - comparitors, decoders, other wide-gate functions n development and programmer support - ict place development software - fitters for abel, cupl and other software - programming support by ict pds-3 and other popu- lar third-party programmers. general description features dip plcc soic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1/clk1 i i i i i vcc i i i i i i i 1/clk2 i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o 1/clk 1 1 1 1 1 1 vcc 1 1 1 1 1 1 1 1clk2 i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o logic control cells global cells i/o cells input cells commercial/ industrial figure 1. pin configuration figure 2. block diagram the pa7128 is a member of the programmable electrically erasable logic ( peel?) array family based on icts cmos eeprom technology. peel? arrays free design- ers from the limitations of ordinary plds by providing the architectural flexibility and speed needed for todays pro- grammable logic designs. the pa7128 offers a versatile logic array architecture with 12 i/o pins, 14 input pins and 36 registers/latches (12 buried logic cells, 12 input regis- ters/latches, 12 buried i/o registers/latches). its logic array implements 50 sum-of-products logic functions that share 64 product terms. the pa7128s logic and i/o cells (lccs, iocs) are extremely flexible offering up to three output functions per cell (a total of 36 for all 12 logic cells). cells are configurable as d, t and jk registers with independent 2
2 of 6 pa7128 this device has been designed and tested for the recom- mended operating conditions. proper operation outside of these levels is not guaranteed. exposure to absolute maxi- mum ratings may cause permanent damage table 2. absolute maximum ratings symbol parameter conditions ratings unit v cc supply voltage relative to ground -0.5 to + 7.0 v v i , v o voltage applied to any pin relative to ground 1 -0.5 to v cc + 0.6 v i o output current per pin (i ol , i oh )25ma t st storage temperature -65 to + 150 c t lt lead temperature soldering 10 seconds +300 c table 3. operating ranges symbol parameter conditions min max unit v cc supply voltage commercial 4.75 5.25 v industrial 4.5 5.5 t a ambient temperature commercial 0 +70 c industrial -40 +85 t r clock rise time see note 2 20 ns t f clock fall time see note 2 20 ns t rvcc v cc rise time see note 2 250 ms table 4. d.c. electrical characteristics symbol parameter conditions min max unit v oh output high voltage - ttl v cc = min, i oh = -4.0ma 2.4 v v ohc output high voltage - cmos v cc = min, i oh = -10a v cc - 0.3 v v ol output low voltage - ttl v cc = min, i ol = 16ma 0.5 v v olc output low voltage - cmos v cc = min, i ol = -10a 0.15 v v ih input high level 2.0 v cc + 0.3 v v il input low level -0.3 0.8 v i il input leakage current v cc = max, gnd v in v cc 10 a i oz output leakage current i/o = high-z, gnd v o v cc 10 a i sc output short circuit current 4 v cc = 5v, v o = 0.5v, t a = 25c -30 -120 ma icc 11 v cc current v in = 0v or v cc 3,11 f = 25mhz all outputs disabled 4 -15 75 (typ.) 19 105 ma -20 105 i-20 115 c in 7 input capacitance 5 t a = 25c, v cc = 5.0v @ f = 1 mhz 6pf c out 7 output capacitance 5 12 pf over the recommended operating conditions
3 of 6 pa7128 symbol parameter 6,12 -15 -20 / i -20 unit min max min max t pdi propagation delay internal (t al + tlc) 912ns t pdx propagation delay external (t ia + t al +t lc + t lo )1520ns t ia input or i/o pin to array input 2 3 ns t al array input to lcc 8 10 ns t lc lcc input to lcc output 10 12ns t lo lcc output to output pin 4 5 ns t od , t oe output disable, enable from lcc output 7 45ns t ox output disable, enable from input pin 7 15 20 ns combinatorial timing - waveforms and block diagram a.c electrical characteristics combinatorial 2
4 of 6 pa7128 symbol parameter 6,12 -20 -20 / i-20 unit min max min max t sci internal set-up to system clock 8 - lcc 14 (t al + t sk + t lc - t ck ) 57ns t scx input 16 (ext.) set-up to system clock, - lcc (t ia + t sci) 710ns t coi system-clock to array int. - lcc/ioc/inc 14 (t ck +t lc ) 79ns t cox system-clock to output ext. - lcc (t coi + t lo )1114ns t hx input hold time from system clock - lcc 0 0 ns t sk lcc input set-up to async. clock 13 - lcc 22ns t ak clock at lcc or ioc - lcc output 1 1 ns t hk lcc input hold time from system clock - lcc 4 4 ns t si input set-up to system clock - ioc/inc 14 (t sk - t ck ) 00ns t hi input hold time from system clock - ioc/inc 14 (t sk - t ck ) 45ns t pk array input to ioc pclk clock 6 7 ns t spi input set-up to pclk clock 17 - ioc/inc (t sk -t pk -t ia ) 00ns t hpi input hold from pclk clock 17 - ioc/inc (t pk +t ia -t sk ) 68ns t sd input set-up to system clock - ioc/inc sum-d 15 (t ia + t al + t lc + t sk - t ck ) 710ns t hd input hold time from system clock - ioc sum-d 0 0 ns t sdp input set-up to pclk clock (t ia + t al + t lc + t sk - t pk ) - ioc sum-d 710ns t hdp input hold time from pclk clock - ioc sum-d 0 0 ns t ck system-clock delay to lcc/iocinc 6 7 ns t cw system-clock low or high pulse width 6 7 ns f max 1 max. system-clock frequency int/int 1/(t sci + t coi ) 83.3 62.5 mhz f max 2 max. system-clock frequency ext/int 1/(t scx + t coi ) 71.4 52.6 mhz f max 3 max. system-clock frequency int/ext 1/(t sci + t cox ) 62.5 47.6 mhz f max 4 max. system-clock frequency ext/ext 1/(t scx + t cox ) 55.5 41.6 mhz f tgl max. system-clock toggle frequency 1/(t cw + t cw ) 83.3 71.4 mhz t pr lcc presents/reset to lcc output 1 2 ns t st input to global cell present/reset ( tia + t al + t pr )1115ns t aw asynch. preset/reset pulse width 8 8 ns t rt input to lcc reg-type (rt) 7 9 ns t rtv lcc reg-type to lcc output register change 1 2 ns t rtc input to global cell register-type change (t rt + t rtv )811ns t rw asynch. reg-type pulse width 10 10 ns t reset power-on reset time for registers in clear state 2 55s a.c. electrical characteristics sequential
5 of 6 pa7128 sequential timing - waveforms and block diagram 1. minimum dc input is -0.5v, however inputs may under-shoot to -2.0v for periods less than 20ns. 2. test points for clock and v cc in t r , t f , t cl , t ch , and t reset are referenced at 10% and 90% levels. 3. i/o pins are 0v or v cc . 4. test one output at a time for a duration of less than 1 sec. 5. capacitances are tested on a sample basis. 6. test conditions assume: signal transition times of 5ns or less from the 10% and 90% points, timing reference levels of 1.5v (unless otherwise specified). 7. t oe is measured from input transition to v ref ? 0.1v (see test loads at end of section 6 for v ref value). t od is measured from input transition to v oh -0.1v or v ol +0.1v. 8. system-clock refers to pin 1 or pin 28 high speed clocks. 9. for t or jk registers in toggle (divide by 2) operation only. 10. for combinatorial and async-clock to lcc output delay. 11. icc for a typical application: this parameter is tested with the device programmed as a 10-bit d-type counter. 12. test loads are specified in section 5 of this data book. 13. async. clock refers to the clock from the sum term (or gate). 14. the lcc term indicates that the timing parameter is applied to the lcc register. the ioc term indicates that the timing parameter is applied to the ioc register. the lcc/ioc term indicates that the tim- ing parameter is applied to both the lcc and ioc registers. the lcc/ ioc/inc term indicates that the timing parameter is applied to the lcc, ioc and inc registers. 15. this refers to the sum-d gate routed to the ioc register for an addi- tional buried register 16. the term input without any reference to another term refers to an (external) input pin. 17. the parameter t spi indicates that the pclk signal to the ioc register is always slower than the data from the pin or input by the absolute value of (t sk -t pk -t ia ). this means that no set-up time for the data from the pin or input is required, i.e. the external data and clock can be sent to the device simultaneously. additionally, the data from the pin must remain stable for t hpi time, i.e. to wait for the pclk signal to arrive at the ioc register. 18. typical (typ) i cc is measured at t a =25 o c, freq = 25mhz, v cc =5v. notes: 2
6 of 6 pa7128 table 2. ordering information part number speed temperature package pa7128p-15 9/15ns c p28 PA7128J-15 j28 pa7128s-15 s28 pa7128p-20 12/20ns c p28 pa7128pi-20 i pa7128j-20 12/20ns c j28 pa7128ji-20 i pa7128s-20 12/20ns c s28 pa7128si-20 i part number device pa7128p-15 package t = plastic 600mil dip j = plastic (j) leaded chip carrier s = soic temperature range (blank) = commercial 0 to 70c i = industrial -40 to +85c speed -15 = 9ns/15ns tpdi/tpdx -20 = 12ns/20ns tpdi/tpdx suffix
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